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FINAL
AM27X128
128 Kilobit (16 K x 8-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
s As an OTP EPROM alternative: -- Factory optimized programming -- Fully tested and guaranteed s As a Mask ROM alternative: -- Shorter leadtime -- Lower volume per code s Fast access time -- 55 ns s Single +5 V power supply s Compatible with JEDEC-approved EPROM pinout s 10% power supply tolerance s High noise immunity s Low power dissipation -- 100 A maximum CMOS standby current s Available in Plastic Dual-In-line Package (PDIP) and Plastic Leaded Chip Carrier (PLCC) s Latch-up protected to 100 mA from -1 V to VCC + 1 V s Versatile features for simple interfacing -- Both CMOS and TTL input/output compatibility -- Two line control functions
GENERAL DESCRIPTION
The AM27X128 is a factory programmed and tested OTP EPROM. It is programmed after packaging prior to final test. Every device is rigorously tested under AC and DC operating conditions to your stable code. It is organized as 16 Kwords by 8 bits per word and is available in plastic dual in-line packages (PDIP), as well as plastic leaded chip carrier (PLCC) packages. ExpressROM devices provide a board-ready memory solution for medium to high volume codes with short leadtimes. This offers manufacturers a cost-effective and flexible alternative to OTP EPROMs and mask programmed ROMs. Data can be accessed as fast as 55 ns, allowing high-performance microprocessors to operate with reduced WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 W in standby mode.
BLOCK DIAGRAM
VCC VSS OE# CE# Output Enable Chip Enable and Prog Logic Y Decoder A0-A13 Address Inputs Output Buffers Data Outputs DQ0-DQ7
Y Gating
X Decoder
131,072 Bit Cell Matrix
12083F-1
Publication# 12083 Rev: F Amendment/0 Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options VCC = 5.0 V 5% VCC = 5.0 V 10% -55 55 55 35 -70 70 70 40 -90 90 90 40 -120 120 120 50 -150 150 150 50 -200 200 200 50 250 250 50 AM27X128 -255
Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)
CONNECTION DIAGRAMS Top View
DIP PLCC
PGM# (P#) A13
A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
PGM# (P#) A13 A8 A9 A11 OE# (G#) A10 CE # (E#) DQ7 DQ6 DQ5 DQ4 DQ3
12083F-2
4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS DU DQ3 DQ4 DQ1 DQ2 DQ5 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE# (G#) A10 CE# (E#) DQ7 DQ6
VCC
A7 A12
VPP
VPP
1
28
VCC
DU
12083F-3
Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don't use (DU) for PLCC.
PIN DESIGNATIONS
A0-A13 CE# (E#) DQ0-DQ7 OE# (G#) PGM# (P#) VCC VPP VSS NC = Address Inputs = Chip Enable Input = Data Input/Outputs = Output Enable Input = Program Enable Input
LOGIC SYMBOL
14 A0-A13 DQ0-DQ7 CE# (E#) 8
= VCC Supply Voltage = Program Voltage Input = Ground = No Internal Connection
12083F-4
OE# (G#)
2
AM27X128
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27X128
-55
J
C
XXXXX
CODE DESIGNATION Assigned by AMD TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE P = 28-Pin Plastic Dual In-Line Package (PD 028) J = 32-Pin Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION AM27X128 128 Kilobit (16 K x 8-Bit) CMOS ExpressROM Device
Valid Combinations AM27X128-55 AM27X128-70 AM27X128-90 AM27X128-120 AM27X128-150 AM27X128-200 AM27X128-255 VCC = 5.0 V 5% PC, JC, PI, JI
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
AM27X128
3
FUNCTIONAL DESCRIPTION Read Mode
To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least t ACC -t OE. Refer to the Switching Waveforms section for the timing diagram.
CE# should be decoded and used as the primary device-selecting function, while OE# be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
Standby Mode
The device enters the CMOS standby mode when CE# is at VCC 0.3 V. Maximum VCC current is reduced to 100 A. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on ExpressROM device arrays, a 4.7 F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
Output OR-Tieing
To accommodate multiple memory connections, a two-line control function provides: s Low memory power dissipation, and s Assurance that output bus contention will not occur.
MODE SELECT TABLE
Mode Read Output Disable Standby (TTL) Standby (CMOS) CE# VIL X VIH VCC 0.3 V OE# VIL VIH X X PGM# X X X X VPP X X X X Outputs DOUT High Z High Z High Z
Note: X = Either VIH or VIL.
4
AM27X128
ABSOLUTE MAXIMUM RATINGS
Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to VSS All pins except VCC . . . . . . . . . -0.6 V to VCC + 0.6 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . -0.6 V to 7.0 V
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .-40C to +85C Supply Read Voltages VCC for 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Note:
1. Minimum DC voltage on input or I/O pins -0.5 V. During voltage transitions, the input may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20ns. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability.
AM27X128
5
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter Symbol VOH VOL VIH VIL ILI ILO ICC1 ICC2 ICC3 Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Active Current (Note 2) VCC TTL Standby Current VCC CMOS Standby Current VIN = 0 V to VCC VOUT = 0 V to VCC CE# = VIL, f = 10 MHz, IOUT = 0 mA CE# = VIH CE# = VCC 0.3 V C/I Devices Test Conditions IOH = -400 A IOL = 2.1 mA 2.0 -0.5 Min 2.4 0.45 VCC + 0.5 +0.8 1.0 1.0 25 1.0 100 Max Unit V V V V A A mA mA A
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied. Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
30 25 20 15 10 1 2 3 4 5 6 7 Frequency in MHz 8 9 10
30 25 20 15 10 -75 -50 -55 0 25 50 75 100 125 150 Temperature in C
12083F-6
Supply Current in mA
12083F-5
Figure 1.
Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25C
Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz
6
AM27X128
Supply Current in mA
TEST CONDITIONS
5.0 V
Table 1.
Test Condition Output Load
Test Specifications
-55, -70 All others Unit
Device Under Test CL 6.2 k
2.7 k
1 TTL gate 30 20 0.0-3.0 1.5 1.5 0.45-2.4 0.8, 2.0 0.8, 2.0 100 pF ns V V V
Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels
Note: Diodes are IN3064 or equivalents.
12083F-7
Input timing measurement reference levels Output timing measurement reference levels
Figure 3.
Test Setup
SWITCHING TEST WAVEFORM
3V 1.5 V 0V Input Output Test Points 1.5 V 0.8 V 0.45 V Input Output 2.4 V 2.0 V Test Points 0.8 V 2.0 V
Note: For CL = 30 pF.
Note: For CL = 100 pF.
12083F-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
KS000010-PAL
AM27X128
7
AC CHARACTERISTICS
Parameter Symbols JEDEC tAVQV tELQV tGLQV tEHQZ tGHQZ Standard tACC tCE tOE tDF (Note 2) Description Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable High or Output Enable High to Output High Z, Whichever Occurs First Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First Test Setup CE#, Max OE# = VIL OE# = VIL Max CE# = VIL Max -55 55 55 35 -70 70 70 40 AM27X128 -90 90 90 40 -120 -150 120 120 50 150 150 50 -200 -255 200 200 50 250 250 50 Unit ns ns ns
Max
25
25
25
30
30
30
30
ns
tAXQX
tOH
Min
0
0
0
0
0
0
0
ns
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is sampled and not 100% tested. 3. Switching characteristics are over operating range, unless otherwise specified. 4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4 Addresses 0.45 CE# tCE OE# tOE High Z tACC (Note 1) tOH Valid Output High Z
12083F-9
2.0 0.8
Addresses Valid
2.0 0.8
tDF (Note 2)
Output
Notes: 1. OE# may be delayed up to tACC - tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter Symbol CIN COUT PD 028 Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 0 VOUT = 0 Typ 5 8 Max 10 10 PL 032 Typ 10 11 Max 12 14 Unit pF pF
Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f = 1 MHz.
8
AM27X128
PHYSICAL DIMENSIONS PD 028--28-Pin Plastic Dual In-Line Package (measured in inches)
1.440 1.480 28 15 .530 .580 14 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .008 .015
.600 .625
Pin 1 I.D.
SEATING PLANE .120 .160 .090 .110 .014 .022 .015 .060
16-038-SB-AG PD 028 DG75 7-13-95 ae
PL 032--32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056
.447 .453
.585 .595 .547 .553
Pin 1 I.D.
SIDE VIEW
16-038FPO-5 PL 032 DA79 6-28-94 ae
AM27X128
9
REVISION SUMMARY FOR AM27X128 Revision F Global
Changed formatting to match current data sheets.
Trademarks Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
10
AM27X128

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